The present invention relates to a ZQ calibration circuit in a semiconductor memory device, and more particularly to a ZQ calibration operation controller circuit for such a ZQ calibration circuit.
Generally, semiconductor memory devices that include an integrated circuit, such as a microprocessor, a memory circuit and a gate array circuit, are used in various electrical appliances, e.g., personal computers, server computers and workstations. As the operating speed of the electrical appliances increases, a swing width of signals transmitted between semiconductor memory devices inside the electrical appliances decreases to minimize a delay time taken to transmit the signals. However, as the swing width decreases, signal transmission is affected by external noise to a greater degree and signal reflection in an interface terminal increases due to impedance mismatching.
The impedance mismatch is caused by variation of the manufacturing process, the supply voltage and the operating temperature (PVT). This impedance mismatch makes it hard to transmit data at high speeds. Because a signal outputted from a semiconductor memory device may be distorted by the impedance mismatch, a malfunction such as a set up/hold failure or a misjudgment of a signal level may be caused in a corresponding semiconductor memory device receiving the distorted signal.
A semiconductor memory device may include an input circuit for receiving external signals through an input pad and an output circuit for outputting internal signals through an output pad. Particularly, a semiconductor memory device operating at a high speed may include an impedance matching circuit for matching interface impedance with another semiconductor memory device near the pads in order to prevent the above malfunctions.
Generally, in a semiconductor memory device transmitting a signal, source termination is performed by an output circuit. In a semiconductor memory device receiving a signal, parallel termination may be performed by a termination circuit connected in parallel to an input circuit.
The ZQ calibration is a process for generating pull-up and pull-down calibration codes that change as PVT conditions change. Resistance values of input and output circuits are calibrated by using the pull-up and pull-down calibration codes. The ZQ calibration is performed in a ZQ calibration circuit described below.
FIG. 1 is a block diagram of a conventional ZQ calibration circuit. The ZQ calibration circuit includes a first pull-up resistance unit 110, a second pull-up resistance unit 120, a pull-down resistance unit 130, a reference voltage generator 102, comparators 103 and 104, and p-code and n-code counters 105 and 106.
A supply voltage VDDQ is divided by the first pull-up resistance unit 110 and a reference resistor 101, thereby providing a voltage to a node ZQ. The reference resistor 101, which is connected to a pin coupled to the node ZQ, generally has a resistance of 240Ω. The comparator 103 compares the voltage at the node ZQ with a reference voltage VREF outputted from the reference voltage generator 102, thereby generating an up/down signal UP/DN. The reference voltage VREF is generally set to half of the supply voltage, i.e. VDDQ/2.
The p-code counter 105 receives the up/down signal UP/DN, thereby generating a binary code PCODE<0:N>. The binary code PCODE<0:N> turns on/off MOS transistors coupled in parallel in the first pull-up resistance unit 110, thereby calibrating resistance of the first pull-up resistance unit 110. The calibrated resistance of the first pull-up resistance unit 110 has an effect on the voltage at the node ZQ. The above operations are repeated. That is, the pull-up calibration is performed in the first pull-up resistance unit 110 so that the resistance of the first pull-up resistance unit 110 becomes identical to that of the reference resistor 101.
The binary code PCODE<0:N> generated during the pull-up calibration is also inputted to the second pull-up resistance unit 120 and determines its resistance. Similarly to the pull-up calibration, a pull-down calibration is performed. A voltage at a node ZQ′ becomes identical to the reference voltage VREF by applying a binary code NCODE<0:N> generated by the comparator 104 and the n-code counter 106. The pull-down calibration is performed so that the resistance of the pull-down resistance unit 130 becomes identical to that of the second pull-up resistance unit 120.
The ZQ calibration includes the pull-up calibration and the pull-down calibration. The binary codes PCODE<0:N> and NCODE<0:N> resulting from the ZQ calibration are inputted to an input or output circuit so as to calibrate the respective resistors of the resistance units. In the case of the semiconductor memory device, the binary codes PCODE<0:N> and NCODE<0:N> determine the resistance of pull-up and pull-down resistors connected to DQ pads. The pull-up and pull-down resistors have a similar layout to the above pull-up and pull-down resistance units.
While an output driver of the semiconductor memory device uses both pull-up and pull-down resistors, an input buffer of the semiconductor memory device uses only a pull-up resistor. In that case, the ZQ calibration circuit includes the pull-up resistance unit 110, the p-code counter 105 and comparator 103. Only the pull-up calibration is then performed.
The ZQ calibration further employs a ZQ calibration controller 107 and a time counter 108 for controlling the ZQ calibration. The ZQ calibration controller 107 generates ZQ calibration signals ZQINIT, ZQOPER and ZQCS according to the type of ZQ calibration. The CAL_OPER signal from the time counter 108 activates the comparators 103 and 104 for a predetermined time according to the ZQ calibration signals ZQINIT, ZQOPER and ZQCS and a clock signal CLK, thereby performing the ZQ calibration.
FIG. 2A is a table showing the logic levels of corresponding signals CKE, /CS, /RAS, /CAS, /WE and A10 according to the types of ZQ calibration. The other signals referred to in the table indicate bank addresses BA3˜BA0 or cell addresses A15˜13, A12, A11 and A9˜0, which have no relation to ZQ calibration in accordance with the present invention. A detailed description of the latter will therefore be omitted. The ZQ calibration is classified into long type ZQ calibration (ZQCL) and short type ZQ calibration (ZQCS). Referring to FIG. 2A, the long and the short type ZQ calibration is determined according to a logic level of a signal A10.
FIG. 2B is a table of timing parameters according to the types of ZQ calibration. According to the circumstances, the ZQ calibration is performed for a relatively long time or for a relatively short time. The former is the long type ZQ calibration and the latter is the short type ZQ calibration. Initial ZQ calibration after a power-up and ZQ calibration performed by a controller during an operation are classified as the long type calibration. Operation cycles tZQINIT and tZQOPER of the initial and operating ZQ calibrations are at least 512 and 256 cycles, respectively. Referring to FIG. 2B, an operation cycle tZQCS of the short type ZQ calibration is at least 64 cycles.
FIG. 3 is a schematic circuit diagram of the ZQ calibration controller 107 described in FIG. 1, and includes logic gates ND1-ND6, delay units 301 and 302, and inverters 303-307.
A ZQ calibration command ZQC is enabled by combining a chip select signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS and a write enable signal /WE (see FIG. 2A). When the ZQ calibration command ZQC is enabled and signal A10 is disabled (at a logic low level), a logic gate ND1 outputs a signal ZQCL at a logic low level and a logic gate ND2 outputs the ZQ calibration signal ZQCS at a logic high level. Accordingly, the short type ZQ calibration is performed in response to the ZQ calibration signal ZQCS.
When the ZQ calibration command ZQC is enabled and the signal A10 is enabled (at a logic high level), the logic gate ND1 outputs the signal ZQCL at a logic high level and the logic gate ND2 outputs the ZQ calibration signal ZQCS at a logic low level. Accordingly, the long type ZQ calibration is performed in response to the signal ZQCL.
When the signal ZQCL is enabled (at a logic high level), the ZQ calibration signal ZQINIT or ZQPOER is enabled. After a semiconductor memory device is powered-up, a signal INIT_STATE is initially at a logic high level. Reset signal RESETb is for resetting the semiconductor memory device, and signal RESET BP_L2H is a delayed reset signal for a predetermined time.
Accordingly, the ZQ calibration signal ZQINIT is enabled (at a high logic level) and the initial ZQ calibration is performed. After a predetermined time, the signal INIT_STATE goes to a logic low level in response to a feedback signal ZQINITb_d. The ZQ calibration signal ZQOPER is enabled. The ZQ calibration is performed in response to the ZQ calibration signal ZQOPER.
FIG. 4 illustrates a signal timing diagram for the operation of the ZQ calibration controller described in FIG. 3. That is, looking at the command (CMD) trace, when the ZQ calibration command ZQC is enabled, the short type ZQ calibration is performed in response to the logic low level of signal A10 and the long type ZQ calibration is performed in response to the logic high level of signal A10. In case of the long type ZQ calibration, the initial ZQ calibration is performed in response to the ZQ calibration signal ZQINIT initially. And then, the ZQ calibration is performed in response to the ZQ calibration signal ZQOPER. The clock waveform is shown at CLK.
FIG. 5 illustrates a signal timing diagram for the voltage levels on the ZQ and ZQ′ nodes of the ZQ calibration circuit shown in FIG. 1, according to the initial ZQ calibration.
The voltage levels converge at half of the supply voltage (VDDQ/2) for the initial ZQ calibration, which is performed in at least 512 cycles. However, in the case of a large variation of PVT, the voltage levels cannot reach the target level during the initial ZQ calibration. Generating the pull-up and the pull-down codes PCODE<0:N> and NCODE<0N:> is therefore not completed, and the input buffer and output driver fail to have a target resistance. In this case, malfunctions are caused by the impedance mismatch. VSSQ is the reference voltage that VDDQ is determined relative to, i.e. the source voltage in the case where VDDQ is the drain voltage.